Ph.D. Department of Electrical and Computer Engineering, Carnegie Mellon University,Pittsburgh, USA, December 2006 Master of Engineering Department of Electronic Engineering, Tsinghua University, Beijing, April 1998 Bachelor of Engineering Department of Electronic Engineering, Tsinghua University, Beijing, July 1995

Associate Professor, School of Software, Tsinghua University, Beijing Mar’13 – present Associate Professor, Institute of Microelectronics, Tsinghua University, Beijing Mar’08 – present Software Architect Magma Design Automation, Mar’05- Mar’08 Senior Software Engineer Incentia Design Automation, May’04 - Mar’05

Invited course expert and editor Parallel Programing for Many-Core Processors, China Excellent Course Center, 2010 – present NVIDIA Partner Professor http://www.nvidia.com/object/professor_partners_bios_yangdong.html Co-chair Int’l Workshop on Frontier of GPU Computing, 2010, 2011, 2012 Guest editor VLSI Design Journal, Jan. 2012 Technical program committee IEEE Computer Society Annual Symposium on VLSI (2009-present), HPC China (2013), ASP-DAC(2012), ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (2010), IEEE/ACM Great Lakes Symposium on VLSI (2010)

National Key Research and Development Program of China “Research and development of an integrated Platform for product lifecycle service”(2018-2021) National Key Scientific Instrument and Equipment Development Project of China National Science Foundation“Multi-Physics Data Driven System Health Analysis Instrument for High-Speed Trains”(2016-2020) Key Research and Development Program of CRRC Corporation Limited “Research and application for fault prediction and health management of railway equipment”(2017-2020) Key Research and Development Program of CRRC Corporation Limited “Remote monitoring and diagnostic system for oversea-operated locomotives.”(2017-2019) The National Key Technology R&D Program of the Ministry of Science and Technology “Technology and system development for train control and information service network (TCSN)”(2015-2017) China CNR Corporation Limited“Development of T1113-based type-5 multifunction vehicle bus equipment”(2013) Self-directed innovation project of Tsinghua University (2012-2014，2018-2019)

Best paper award, International Conference on Computer Design, 2013 NVIDIA Partner Professor Award, 2009 - 2018 Foundation for Key Faculty Members, Tsinghua University, 2008 Deng Feng Foundation, 2008 #1 in PASCAL VOC Challenge (Object detection track), 2017 #1 in MS Coco Challenge (Object detection track), 2017 #1 in CVPR WAD Challenge (Object detection track), 2018

Books 1. Y. Deng, H. Chen, and Y. Liu, “Parallel Programming for Many-Core Processors,” Higher Education Publishing House, 2014. 2. Y. Deng and W. Maly, “3-D VLSI – A 2.5-D Integration Scheme,” Springer Verlag/Tsinghua University Publishing House, 2010. 3. Z. Wang and Y. Deng, “Structural VLSI Design and High Level Synthesis,” Tsinghua Publishing House, 1998. Survey Papers 1. Y. Deng and S. Mu, “A Survey on GPU Based Electronic Design Automation Computing,” Invited Paper, Foundation and Trends in Electronics Design Automation, Now Publishers, 2013. 2. Y. Deng, D. Wang, and Y. Zhu, “Asynchronous Parallel Logic Simulation on Modern Graphics Processors,” Why Scientists and Engineers Need GPUs, Springer, 2012. 3. Y. Deng, “Hardware/Software Co-Design for System-on-Chips,” Communications of China Computer Federation, Feb. 2012. 4. Y. Deng, "GPU Accelerated VLSI Design Verification," Invited paper, First International Workshop on Frontier of GPU Computing, Jun. 2010. Representative Conference Publications 1. Zeming Li, Chao Peng, Gang Yu, Xiangyu Zhang, Yangdong Deng, Jian Sun, DetNet: A Backbone network for Object Detection, ECCV, 2018. 2. J. Huang, Y. Gao, S. Lu, X. Zhao, Y. Deng, and M. Gu, Energy-Efficient Automatic Train Driving by Learning Driving Patterns, AAAI, 2018. 3. Z. Li, Y. Chen, G. Yu, and Y. Deng, R-FCN++: Towards Accurate Region-based Fully Convolutional Networks for Object Detection, AAAI, 2018. 4. Z. Li, L. Liu, Y. Deng, S. Yin, Y. Wang, and S. Wei, Aggressive Parallelization of Irregular Applications on Reconfigurable Architectures, 44th International Symposium on Computer Architecture (ISCA), Toronto, Canada, 2017. 5. Z. Li, Y. Deng, and M. Gu: Path compression kd-trees with multi-layer parallel construction a case study on ray tracing. ACM SIGGRAPH Symposium on Interactive 3D Graphics and Games (I3D), 2017. 6. X. Wang, Y. Deng, G. Zhang, and Z. Wang, Apparent resolution enhancement for near-eye light field display, SIGGRAPH Asia Mobile Graphics and Interactive Applications, 2015. 7. Y. Wang, C. Liu, and Y. Deng, A feasibility study of ray tracing on mobile GPUs, SIGGRAPH Asia 2014 Mobile Graphics and Interactive Applications, 2014. 8. T. Wang and Y. Deng, Mining Effective Parallelism from Hidden Coherence for GPU Based Path Tracing, SIGGRAPH Asia, 2013. 9. K. Fang, Y. Ni, J. He, Z. Li, S. Mu, and Y. Deng, FastLane: An FPGA Accelerated GPU Microarchitecture Simulator, IEEE International Conference on Computer Design, 2013. 10. Y. Deng, B. Wang, and S. Mu, "Taming Irregular EDA Applications on GPUs," IEEE/ACM International Conference on Computer-Aided Design, Nov. 2009. Representative Journal Publications 1. Y. Deng and S. Mu, “A Survey on GPU Based Electronic Design Automation Computing,” Invited Paper, Foundation and Trends in Electronics Design Automation, Now Publishers, 2013. 2. S. Mu, Y. Deng, et. al. “Orchestrating Cache Management and Memory Scheduling for GPGPU Applications”, IEEE Transaction on Very Large Scale Integration, 2014. 3. Y. Jiang, H. Zhang, Z. Li, Y. Deng, X. Song, M. Gu, and J.-G. Sun: Design and Optimization of Multiclocked Embedded Systems Using Formal Techniques. IEEE Trans. Industrial Electronics 62(2): 1270-1278 (2015). 4. J. Huang, Y. Deng, Q. Yang, J. Sun, An Energy- Efficient Train Control Framework for Smart Railway Transportation: IEEE Transactions on Computers 65, no. 5 (2016): 1407-1417. 5. Y. Deng, Y. Ni, Z. Li, S. Mu S. and W. Zhang, Toward Real-Time Ray Tracing: A Survey on Hardware Acceleration and Microarchitecture Techniques, ACM Computing Surveys, 2017. 6. Y. Lu, L. Liu, Leibo, Y. Deng, J. Weng, S. Yin, Y. Shi, S. Wei, Triggered-Issuance and Triggered-Execution: A Control Paradigm to Minimize Pipeline Stalls in Distributed Controlled Coarse-Grained Reconfigurable Arrays, IEEE Transactions on Parallel and Distributed Systems, 2018. 7. J. Huang, Q. Huang, Y.Deng, and Y.-H. Chen. “Toward Robust Vehicle Platooning With Bounded Spacing Error.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 36, no. 4 (2017): 562-572. 8. Z. Li , L. Liu , Y. Deng, S.Yin , and S. Wei, Breaking the Synchronization Bottleneck with Reconfigurable Transactional Execution, IEEE Computer Architecture Letters, Vol.17, No. 2, July-Dec. 1 2018. 9. Y. Lu, L. Liu, Leibo, Y. Deng, J. Weng, S. Yin, Y. Shi, S. Wei, Triggered-Issuance and Triggered-Execution: A Control Paradigm to Minimize Pipeline Stalls in Distributed Controlled Coarse-Grained Reconfigurable Arrays, Accepted, IEEE, Transactions on Parallel and Distributed Systems. (可重构计算机) 10. Z.Li, H. Wang, Y. Deng, X. Zhao, Y. Gao, X. Song, and M. Gu. Time-triggered Switch-Memory-Switch Architecture for Time-Sensitive Networking Switches. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2018.